1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and more particularly to a structure of a memory cell array suitable to higher integration of a nonvolatile semiconductor memory device capable of electric rewriting.
2. Description of Related Art
Since a flash memory as one of nonvolatile semiconductor memory devices is excellent in portability, impact resistance and capable of electrically erasing collectively, a demand therefor has been increased rapidly in recent years as a memory device for small-sized portable information equipments such as portable personal computers or portable telephones.
In the flash memory, lowering of the bit cost is an important subject and, for attaining this, there has been proposed a method of decreasing the number of contact holes and global bit lines thereby decreasing the chip area by improving the layout not only for the memory cells but also for selection transistors.
In the existent NAND type flash memory, two active regions are connected, and are connected by way of contact holes to global bit lines, and first selection transistors for selecting two memory cell strings disposed in each of the active regions are arranged in two rows with gate wirings thereof being in parallel. The selection transistors in each row are constituted by serially connecting enhancement type transistors and depletion type transistors alternately. Further, the source line is disposed in perpendicular to the active region, second selection transistors are disposed in one row so as to be connected with the source line, and a plurality of memory cell transistors each having a first gate and a second gate are connected in series between the first selection transistors in two rows and the second selection transistors in one row (for example, refer to Patent Document 1 infra).
Alternatively, there is a method of constituting selection transistors only with enhancement type transistors by separately disposing the first selection transistors and the second selection transistors, thereby saving ion implantation for forming depletion type transistors and thereby simplifying the production steps (for example, refer to Patent Document 2 infra).
In the two examples of the Patent Document 1 and the Patent Document 2 described above, two rows of selection transistors and two contact holes necessary for connection of two rows of the active regions with a common global bit line are simplified into selection transistors in two rows and one contact hole, thereby decreasing the area in the direction of bit line and reducing the chip area.
[Patent Document 1]
                JP-A No. 74069/1990[Patent Document 2 ]        JP-A No. 46159/1996        
However, in the two patent documents described above, a method of decreasing the area for the selection transistor portion per se is not disclosed.